1. Field of the invention
The present invention relates to an electrically erasable programmable non-volatile semiconductor memory, and a method for manufacturing the same.
2. Description of Related Art
Of electrically erasable programmable non-volatile semiconductor memories, a memory including a plurality of memory cells and having a function of simultaneously erasing the memory cells as a whole, is called a "flash memory". For example, this type memory is described in M. Momodomi et al "NEW DEVICE TECHNOLOGIES; FOR 5 V-ONLY Mb EEPROM WITH NAND STRUCTURE CELL", IEDM 88, pp412-415, (1988 IEEE) and in H. Onoda et al "A NOVEL CELL STRUCTURE SUITABLE FOR A 3 VOLT OPERATION, SECTOR ERASE FLASH MEMORY", IEDM 92, pp 599-602 (1992 IEEE), the disclosure of which is incorporated by reference in their entirety into the present application.
Referring to FIG. 1, there is shown a circuit diagram illustrating one conventional example of this type non-volatile semiconductor memory. The shown example includes sixteen memory cells M.sub.11 to M.sub.18 and M.sub.21 to M.sub.28 which are controlled through eight row lines (word lines W.sub.1 to W.sub.8) and two main column lines (main bit lines B.sub.1 and B.sub.2). The eight row lines W.sub.1 to W.sub.8 and the two main column lines B.sub.1 and B.sub.2 are divided into first four row lines W.sub.1 to W.sub.4 and second four row lines W.sub.5 to W.sub.8, and a first main column line B.sub.1 and a second main column line B.sub.2, respectively, so that the whole of the memory is divided into four blocks BK.sub.11 to BK.sub.22.
In the blocks BK.sub.11 to BK.sub.2, sub colunto lines (sub bit lines SB.sub.1 to SB.sub.4) are provided respectively in addition to the main column lines. Each of the sub column lines is connected to the memory cells in a corresponding block, and is connected through a selection transistor ST.sub.1 to ST.sub.4 to a corresponding one of the main column lines. Any block can be selected by supplying a voltage signal to a selection line S.sub.1 or S.sub.2 so that a corresponding selection transistor ST.sub.1 to ST.sub.4 is turned on to transfer a potential of the main column line to the sub column line connected to the turned-on selection transistor. Provision of these selection transistors ST.sub.1 to ST.sub.4 makes it possible to completely isolate the memory cells in units of block.
In the blocks, a source of the memory cells M.sub.11 to M.sub.18 and M.sub.21 to M.sub.28 are connected to source lines G.sub.1 or G.sub.2. Incidentally, the row lines W.sub.1 to W.sub.8 and the selection lines S.sub.1 and S.sub.2 are controlled by a row decoder PC.sub.1, and the main column lines B.sub.1 and B.sub.2 are controlled by a peripheral circuit PC.sub.2 including a column decoder, sense amplifiers and a write circuit which are not shown in the drawing.
Here, referring to FIGS. 2, 3A and 3B, FIG. 2 illustrates a layout pattern diagram of an actual flash memory having the circuit construction shown in FIG. 1, and FIGS. 3A and 3B shows diagrammatic sectional views taken along; the lines A--A and B--B in FIG. 2. In this conventional structure, the memory cell has a stacked gate structure having a floating gate electrode 41a and a control gate electrode 6a, and on file other hand, the selection transistor has an ordinary MOS structure including a gate electrode which also function as a selection line 6b corresponding to for example the selection line S.sub.1 in FIG. 1.
Now, a conventional process for manufacturing the memory cell and the selection transistor will be described with reference to FIGS. 4A to 4D illustrating a process for manufacturing the memory cell and FIG. 5A to 5D illustrating a process for manufacturing the selection transistor.
First, as shown in FIGS. 4A and 5A, on a principal surface of a P-type silicon substrate having the concentration of 10.sup.16 to 10.sup.17 cm.sup.-3, a device isolation structure (field oxide film 2) is formed so as to partition first and second device formation regions. A first gate insulator film 31 having a thickness of about 10 nm is formed in the first device formation region, and a second gale insulator film 32 having a thickness of about 20 nm is formed in the second device formation region.
Furthermore, a first floating gate polysilicon film 41 is formed to cover the first device formation region, corresponding to the memory cell and a neighboring region surrounding the first device formation region. Thereafter, as shown in FIGS. 4A and 5B, a third insulator film 5 is formed to cover the first floating gate polysilicon film 41, and a second polysilicon film 6 is formed to cover the third insulator film 5 and the second gate insulator film 32 in the second device formation region.
Then, as shown in FIGS. 4C and 5C, a first photoresist layer 71 and 72 is formed on a selected area of the second polysilicon film 6 within the first and second device formation regions. Within the first device formation region, the second polysilicon film 6, the third gate insulator film 5 and the first floating gate polysilicon film 41 are etched in the named order, so as to form a stacked gate structure composed of a floating gate electrode 41a, a floating gate upper insulator film 5a and a control gate electrode 6a, as well as a word line 6a (corresponding to the row line W.sub.1) for interconnecting the control gate electrode of the memory cells arranged in line in a row direction. Furthermore, arsenic (As) is implanted to the silicon substrate principal surface within the first device formation region which is not covered with the stacked structure, so that high impurity concentration N-type diffused layers 91s and 91d are formed.
Finally, as shown in FIGS. 4D and 5D, a photoresist layer 101 and 102 is formed on a selected area or the second polysilicon film 6 within the first and second device formation regions, and an etching is performed using the photoresist layer as a mask, so as to form a selection line 6b (corresponding to the selection line S.sub.1) which also acts as a selection gate electrode. In addition, arsenic (As) is implanted to the silicon substrate principal surface which is not covered with the selection line 6b, so that high impurity concentration N-type diffused layers 92s and 92d are formed. Thereafter, as shown in FIGS. 3A and 3B, an interlayer insulating film 15 is deposited, and a contact hole C.sub.1 is formed. Further, a first layer aluminum alloy film 16 is deposited and then patterned to as to form a source line 16 (corresponding to the source line G.sub.1) and a sub bit line 16 (corresponding to the sub column line SB.sub.1). Then, an interlayer insulating film 17 is deposited, and a contact hole C.sub.2 is formed, and further, a second layer aluminum alloy film 18 is deposited and then patterned to as to form a main bit line 18 (corresponding to the column line B.sub.1).
Now, another conventional process for manufacturing the memory cell and the selection transistor will be described with reference to FIGS. 6A to 6D illustrating a process; for manufacturing the memory cell and FIG. 7A to 7D illustrating a process for manufacturing the selection transistor.
First, as shown in FIGS. 6A and 7A, on a principal surface of a P-type silicon substrate, a field oxide film 2 is formed so as to partition first and second device formation regions. A first gate insulator film 31 having a thickness of about 10 nm is formed in the first device formation region, and a second gate insulator film 32 having a thickness of about 20 nm is formed in the second device formation region.
Furthermore, first and second floating gate polysilicon films 41 and 42 are formed to cover the first and second device formation regions and a neighboring region surrounding the first and second device formation regions. Thereafter, a third gate insulator film 5 is formed to cover the whole of the substrate principal surface, and a photoresist layer 11 having an opening 12 on the third insulator film 5 above the second floating gate polysilicon film 42, is formed. The third insulator film 5 in the opening 12 of the photoresist layer 11 is etched, so that a contact hole 13 is formed as shown in FIG. 7B. In the first device formation region for the memory cell, no contact hole is formed as shown in FIG. 6B.
Thereafter, as shown in FIGS. 6C and 7C, a second polysilicon film 6 is formed to cover the whole surface. Here, in second device formation region for the selection transistor, the second polysilicon film 6 is connected to the second floating gate polysilicon film 42 through the contact hole 13.
Then, as shown in FIGS. 6C and 7C, a photoresist layer 141 and 142 is formed on a selected area within the first and second device formation regions. The second polysilicon film 6, the second gate insulator film 5 and the first and second floating gate polysilicon films are etched in the named order, so as to form stacked gate structures 81 and 82 as shown in FIGS. 6D and 7D, as well as a word line and a selection line. Finally, arsenic (As) (N-type impurity) is implanted to the silicon substrate principal surface, so that high impurity concentration diffused layers 91s and 91d and 92s and 92d are formed. Thereafter, sub bit lines SB.sub.1 and SB.sub.2, source lines G.sub.1 and G.sub.2, and main bit lines B.sub.1 and B.sub.2 are formed.
Now, an writing (namely, programming) operation of the above mentioned type of memory cell cell will be described. In this memory cell having the stacked gate structure, the memory operation is performed by changing the threshold level between a low threshold level condition (about 2 V) and a high threshold level condition (about 7 V). As one example, it is assumed that the low threshold level condition is a written condition and the high threshold level condition is an erased condition.
In order to bring the memory cells M.sub.11 to M.sub.14 and M.sub.21 to M.sub.24 into the erased condition, for example, the main bit lines B.sub.1 and B.sub.2, the P-silicon substrate 1 and the source lines G.sub.1 and G.sub.2 are all brought to 0 V (ground potential). Furthermore, 15 V is applied to only the word lines W.sub.1 to W.sub.4, and the other word lines W.sub.5 to W.sub.8 are set at 0 V.
In addition, the first and second selection lines S.sub.1 and S.sub.2 are set to 5 V, respectively. Thus, in the memory cells M.sub.11 to M.sub.14 and M.sub.21 to M.sub.24, electrons are injected from the P-silicon substrate to the floating gate through the first gate insulator film between the floating gate and the silicon substrate.
On the other hand, in the case of selecting and writing for example the memory cell M.sub.14, the main bit line B.sub.1 is brought to 5 V, and the main bit line B.sub.2, the P-silicon substrate 1, and the source lines G.sub.1 and G.sub.2 are all set to 0 V. -13 V is applied to only the control gate electrode of the memory cell M.sub.14 (word line W.sub.4), and the other word lines W.sub.1 to W.sub.3 an W.sub.5 to W.sub.8 are set to 0 V. The first and second selection lines S.sub.1 and S.sub.2 are set to 5 V and 0 V, respectively. In this case, -18 V is applied between the drain region (91d) of the memory cell M.sub.14 and the control gate W.sub.4, so that electrons are discharged from the floating gate to the silicon substrate through the first gate insulator film between the floating gate and the silicon substrate.
As the result of the fact that the electrons has been drawn from the floating gate, the potential of the floating gate electrode is caused to elevate to a positive level. Therefore, the threshold of the memory cell M.sub.14 is shifted toward a negative direction. As mentioned above, the threshold level of the written memory cell is ordinarily set on the order of 2 V.
In the above mentioned non-volatile semiconductor memory, the memory cells have the stacked gate structure including the floating gate electrode, but the selection transistor is constituted of either the ordinary MOS transistor or the transistor having a structure which is similar to that of the memory cell but in which the floating gate electrode is interconnected to the control gate electrode. The reason for this is as follows: The selection transistor is provided for connecting the sub bit line in each block to the corresponding main bit line, and therefore, the potential on the main bit line is given to the sub line line through the selection transistor. Therefore, the selection transistor is required to operate with a ceaselessly constant threshold voltage.
In the transistor having the floating gate structure as the memory cell, on the other hand, the threshold of the transistor varies because electric charges are accumulated in the floating gate. In an ordinary reading operation under a voltage lower than the writing voltage, electric charges are gradually slightly injected, with the result that it is not possible to avoid the change of the threshold. Here, even if it is assumed that the selection transistor is constituted to have the same floating structure as that of the memory cell, the electric charges are gradually injected in the ordinary reading operation, with the result that the threshold voltage varies and finally malfunction occurs.
From another viewpoint, the fact that the ordinary MOS transistor is formed in proximity of the above mentioned memory cell, has the following problems:
First, the number of necessary manufacturing steps is large. This is particularly remarkable in the case that the selection transistor is constituted of the ordinary MOS transistor in accordance with the process described with reference to FIGS. 4A to 4D and 5A to 5D. In this process, the memory cell and the selection transistor cannot be in common to each other in most of necessary manufacturing steps. For example, in order to form the polysilicon film for the floating gate only on the first device formation region and its neighboring area, the first polysilicon film is deposited to cover the whole surface, and thereafter, is removed from the region (including the second device formation regions) other than the first device formation region and its neighboring area, so that the first polysilicon film is left only on the-first device formation region and its neighboring area.
In addition, the source/drain diffused regions for the memory cell and the source/drain diffused regions for the selection transistor are formed in a process independent of each other. Therefore, it is not possible to avoid the increase of the number of necessary manufacturing steps as a whole.
In the case that the selection transistor is constituted of the transistor having the structure similar to that of the memory cell but including the floating gate electrode connected to the control gate electrode, in accordance with the process described with reference to FIGS. 6A to 6D and 7A to 7D, on the other hand, the memory cell and the selection transistor can be in common to each other in most of necessary manufacturing steps, and therefore, the number of necessary manufacturing steps can be greatly reduced. In this case, however, the lithographic steps (including a photoresist deposition, exposure, development, etching and resist removing) are increased. In addition, since the contact hole for connecting the selection line to the floating gate electrode is formed, it is not possible to reduce the size of the gate electrode of the selection transistor to a value less than the size of the contact hole plus the mask alignment margin.